Senior Digital Static Timing Analysis Engineer

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JOB DESCRIPTION

We are looking for a highly skilled and motivated Senior Digital Static Timing Analysis Engineer to join our team. As part of our design process, you will be responsible for performing static timing analysis (STA) on digital circuits to ensure they meet the required performance, timing, and reliability criteria.

You will work closely with design, and physical design teams to identify and resolve timing issues in complex integrated circuits (ICs).

This position offers the opportunity to work on cutting-edge technologies for our highly complex SoC and image pipeline development projects.

QUALIFICATIONS

Master’s or Bachelor’s degree in Electrical Engineering or comparable
Minimum 5 years of experience in digital static timing analysis for complex hierarchical SoC designs
Programming skills in script languages (TCL, Perl, Python) are advantageous
Proficiency with STA tools like Cadence Tempus or Synopsys PrimeTime
Strong understanding of digital design principles, including timing, setup/hold, clock domain crossing, clock skew, and IO timing
Knowledge of RTL design languages (Verilog, VHDL) and digital design flows
Understanding of physical design aspects related to timing (e.g., floorplanning, placement, routing, hierarchical designs)
Experience in the field of functional safety is an advantage
Fluent in English, both written and spoken

CONTACT

Please send your application by email, together with your résumé (CV) to:
career(at)dreamchip.de

Dream Chip Technologies GmbH
Steinriede 10
30827 Garbsen
Deutschland

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